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merge: 交換得分十位數與個位數 & bonus ball(#3)

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Reviewed-on: #3
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snsd0805 2021-01-11 11:44:15 +08:00
commit 082b264495
1 changed files with 71 additions and 5 deletions
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74
FPGA_FINAL.v
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@ -26,6 +26,9 @@ module FPGA_FINAL(
reg handsOn; // bool，紀錄球現在丟出去了沒
reg gameOverFlag;
reg showBonus; // bool 顯示額外球
reg Bonus_x, Bonus_y; // 額外球的位子
initial
begin
@ -48,6 +51,8 @@ module FPGA_FINAL(
gameOverFlag = 0;
showBonus = 0;
end
@ -59,6 +64,7 @@ module FPGA_FINAL(
integer ballTime;
integer doubleTime;
// 判斷 所有操作
always @(posedge buttonclk)
begin
@ -86,6 +92,7 @@ module FPGA_FINAL(
upPosition = 1; // 預設為 向上
horizonPosition = 0; // 預設為 正中間方向
showBonus = 0;
end
@ -211,7 +218,7 @@ module FPGA_FINAL(
if(blockSecond[ball_position]==1)
begin
count_digit <= count_digit + 1'b1;
if(count_digit == 4'b1010)
if(count_digit == 4'b1001)
begin
count_digit <= 4'b0;
count_ten = 1;
@ -235,7 +242,7 @@ module FPGA_FINAL(
if(blockFirst[ball_position]==1)
begin
count_digit <= count_digit + 1'b1;
if(count_digit == 4'b1010)
if(count_digit == 4'b1001)
begin
count_digit <= 4'b0;
count_ten = 1;
@ -252,6 +259,46 @@ module FPGA_FINAL(
end
end
end
//
if(doubleTime<200 && showBonus == 0 && handsOn == 0)
doubleTime <= doubleTime+1;
else
begin
if(handsOn == 0)
begin
doubleTime <= 0;
showBonus = 1;
Bonus_x = plat_position + 1;
Bonus_y = 1;
// Bonus ball 撞到第一排磚塊
if((Bonus_y == 6 && blockSecond[Bonus_x] == 1))
begin
count_digit <= count_digit + 1'b1;
if(count_digit == 4'b1001)
begin
count_digit <= 4'b0;
count_ten = 1;
end
blockSecond[Bonus_x] = 0;
showBonus = 0;
end
end
// Bonus ball 撞到第二排磚塊
if((Bonus_y == 7 && blockFirst[Bonus_x] == 1))
begin
count_digit <= count_digit + 1'b1;
if(count_digit == 4'b1001)
begin
count_digit <= 4'b0;
count_ten = 1;
end
blockSecond[Bonus_x] = 0;
showBonus = 0;
end
else
Bonus_y <= Bonus_y + 1;
end
end
end
@ -316,6 +363,25 @@ module FPGA_FINAL(
else
led[8:15] = 8'b11111111;
// 畫 Bonus ball
if(showBonus == 1)
if(row==Bonus_x)
begin
reg [7:0] map;
case(ball_y_position)
3'b000: map = 8'b11111110 ;
3'b001: map = 8'b11111101 ;
3'b010: map = 8'b11111011 ;
3'b011: map = 8'b11110111 ;
3'b100: map = 8'b11101111 ;
3'b101: map = 8'b11011111 ;
3'b110: map = 8'b10111111 ;
3'b111: map = 8'b01111111 ;
endcase
led[0:7] = map;
led[16:23] = map;
end
//開始畫磚塊
led[16:23] = {~blockFirst[row], ~blockSecond[row], 6'b111111};
@ -323,12 +389,12 @@ module FPGA_FINAL(
if(count_digit_enable == 0)
begin
count_digit_enable = 1;
COM = 2'b10;
COM = 2'b01;
end
else
begin
count_digit_enable = 0;
COM = 2'b01;
COM = 2'b10;
end
end