diff --git a/FPGA_FINAL.v b/FPGA_FINAL.v
index b00e4d7..c32a8dd 100644
--- a/FPGA_FINAL.v
+++ b/FPGA_FINAL.v
@@ -196,18 +196,3 @@ module buttondivfreq(input CLK, output reg CLK_div);
 	end
 endmodule
 
-
-// 球 飛行用的除頻器
-module balldivfreq(input CLK, output reg CLK_div);
-	reg[26:0] Count;
-	always @(posedge CLK)
-	begin
-		if(Count>10000000)
-			begin
-				Count <= 27'b0;
-				CLK_div <= ~CLK_div;
-			end
-		else
-			Count <= Count + 1'b1;
-	end
-endmodule
\ No newline at end of file