From 462bd94a2aa1b5221f302cbc9826acf676f7d760 Mon Sep 17 00:00:00 2001 From: snsd0805 Date: Sun, 10 Jan 2021 00:07:19 +0800 Subject: [PATCH] =?UTF-8?q?refactor:=20=E5=88=AA=E9=99=A4=E4=B8=8D?= =?UTF-8?q?=E5=BF=85=E8=A6=81=E7=9A=84=E9=99=A4=E9=A0=BB=E5=99=A8?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- FPGA_FINAL.v | 15 --------------- 1 file changed, 15 deletions(-) diff --git a/FPGA_FINAL.v b/FPGA_FINAL.v index b00e4d7..c32a8dd 100644 --- a/FPGA_FINAL.v +++ b/FPGA_FINAL.v @@ -196,18 +196,3 @@ module buttondivfreq(input CLK, output reg CLK_div); end endmodule - -// 球 飛行用的除頻器 -module balldivfreq(input CLK, output reg CLK_div); - reg[26:0] Count; - always @(posedge CLK) - begin - if(Count>10000000) - begin - Count <= 27'b0; - CLK_div <= ~CLK_div; - end - else - Count <= Count + 1'b1; - end -endmodule \ No newline at end of file