This commit is contained in:
eeeXun 2021-01-10 21:28:21 +08:00
commit 4637bb895c

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@ -211,7 +211,7 @@ module FPGA_FINAL(
if(blockSecond[ball_position]==1)
begin
count_digit <= count_digit + 1'b1;
if(count_digit == 4'b1010)
if(count_digit == 4'b1001)
begin
count_digit <= 4'b0;
count_ten = 1;
@ -235,7 +235,7 @@ module FPGA_FINAL(
if(blockFirst[ball_position]==1)
begin
count_digit <= count_digit + 1'b1;
if(count_digit == 4'b1010)
if(count_digit == 4'b1001)
begin
count_digit <= 4'b0;
count_ten = 1;