commit
47481008a6
65
FPGA_FINAL.v
65
FPGA_FINAL.v
@ -4,7 +4,9 @@ module FPGA_FINAL(
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output reg [0:27] led,
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output reg [0:27] led,
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input left, right,
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input left, right,
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input throw,
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input throw,
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output testLED
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output testLED,
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output reg a,b,c,d,e,f,g,
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output reg [0:1] COM
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);
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);
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reg [7:0]blockFirst = 8'b11111111;
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reg [7:0]blockFirst = 8'b11111111;
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@ -13,6 +15,9 @@ module FPGA_FINAL(
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reg [2:0]plat_position; // 板子位置
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reg [2:0]plat_position; // 板子位置
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reg [2:0]ball_position; // 球 位置
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reg [2:0]ball_position; // 球 位置
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reg [2:0]ball_y_position; // 球 y 座標
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reg [2:0]ball_y_position; // 球 y 座標
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reg [3:0]count_digit; //個位數分數
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reg count_ten; //十位數分數
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reg upPosition;
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reg upPosition;
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integer horizonPosition;
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integer horizonPosition;
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@ -31,6 +36,8 @@ module FPGA_FINAL(
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ball_position = 3'b011; // 預設在 x=3 的位置
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ball_position = 3'b011; // 預設在 x=3 的位置
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ball_y_position = 3'b010; // 預設在 y=1 的位置
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ball_y_position = 3'b010; // 預設在 y=1 的位置
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handsOn = 1; // 預設為 為丟出狀態
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handsOn = 1; // 預設為 為丟出狀態
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count_digit = 4'b0; // 分數預設0
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count_ten = 0;
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upPosition = 1; // 預設為 向上
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upPosition = 1; // 預設為 向上
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horizonPosition = 0; // 預設為 正中間方向
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horizonPosition = 0; // 預設為 正中間方向
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@ -179,10 +186,16 @@ module FPGA_FINAL(
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// // 判斷特殊狀態
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// // 判斷特殊狀態 , 撞到第一排磚塊
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if(ball_y_position==6)
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if(ball_y_position==6)
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if(blockSecond[ball_position]==1)
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if(blockSecond[ball_position]==1)
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begin
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begin
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count_digit <= count_digit + 1'b1;
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if(count_digit == 4'b1010)
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begin
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count_digit <= 4'b0;
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count_ten = 1;
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end
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blockSecond[ball_position] = 0;
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blockSecond[ball_position] = 0;
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if(upPosition) upPosition = 0;
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if(upPosition) upPosition = 0;
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@ -197,10 +210,16 @@ module FPGA_FINAL(
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if(upPosition) ball_y_position <= ball_y_position +1;
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if(upPosition) ball_y_position <= ball_y_position +1;
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else ball_y_position <= ball_y_position -1;
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else ball_y_position <= ball_y_position -1;
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end
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end
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// // 判斷特殊狀態
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// // 判斷特殊狀態 , 撞到第二排磚塊
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if(ball_y_position==7)
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if(ball_y_position==7)
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if(blockFirst[ball_position]==1)
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if(blockFirst[ball_position]==1)
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begin
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begin
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count_digit <= count_digit + 1'b1;
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if(count_digit == 4'b1010)
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begin
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count_digit <= 4'b0;
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count_ten = 1;
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end
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blockFirst[ball_position] = 0;
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blockFirst[ball_position] = 0;
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upPosition = 0;
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upPosition = 0;
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@ -221,6 +240,7 @@ module FPGA_FINAL(
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always @(posedge divclk)
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always @(posedge divclk)
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begin
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begin
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reg [0:2]row;
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reg [0:2]row;
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reg count_digit_enable;
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// 跑 0~7 行
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// 跑 0~7 行
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if(row>=7)
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if(row>=7)
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@ -265,6 +285,42 @@ module FPGA_FINAL(
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//開始畫磚塊
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//開始畫磚塊
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led[16:23] = {~blockFirst[row], ~blockSecond[row], 6'b111111};
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led[16:23] = {~blockFirst[row], ~blockSecond[row], 6'b111111};
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// 顯示分數
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if(count_digit_enable == 0)
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begin
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count_digit_enable = 1;
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COM = 2'b10;
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end
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else
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//begin
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count_digit_enable = 0;
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COM = 2'b01;
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//end
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// 顯示個位
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if(count_digit_enable == 0)
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begin
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case(count_digit)
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4'b0000:{a,b,c,d,e,f,g}=7'b0000001;
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4'b0001:{a,b,c,d,e,f,g}=7'b1001111;
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4'b0010:{a,b,c,d,e,f,g}=7'b0010010;
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4'b0011:{a,b,c,d,e,f,g}=7'b0000110;
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4'b0100:{a,b,c,d,e,f,g}=7'b1001100;
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4'b0101:{a,b,c,d,e,f,g}=7'b0100100;
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4'b0110:{a,b,c,d,e,f,g}=7'b0100000;
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4'b0111:{a,b,c,d,e,f,g}=7'b0001111;
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4'b1000:{a,b,c,d,e,f,g}=7'b0000000;
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4'b1001:{a,b,c,d,e,f,g}=7'b0000100;
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endcase
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end
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// 顯示十位
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else
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begin
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case(count_ten)
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1'b0:{a,b,c,d,e,f,g}=7'b0000001;
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1'b1:{a,b,c,d,e,f,g}=7'b1001111;
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endcase
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end
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end
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end
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endmodule
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endmodule
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@ -298,5 +354,4 @@ module buttondivfreq(input CLK, output reg CLK_div);
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else
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else
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Count <= Count + 1'b1;
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Count <= Count + 1'b1;
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end
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end
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endmodule
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endmodule
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