snsd0805/FPGA_FINAL
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Fix typo

Browse Source
This commit is contained in:
eeeXun 2021-01-14 13:56:25 +08:00
parent 04ebc6a021
commit 83d7b2205f
1 changed files with 10 additions and 7 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

17
FPGA_FINAL.v
View File

@ -8,7 +8,7 @@ module FPGA_FINAL(
input show_two_row, input show_two_row,
output testLED, output testLED,
output reg a,b,c,d,e,f,g, output reg a,b,c,d,e,f,g,
output reg [0:1] COM output reg [0:3] COM
); );
reg [7:0]blockFirst = 8'b11111111; reg [7:0]blockFirst = 8'b11111111;
@ -290,9 +290,12 @@ module FPGA_FINAL(
if(blockSecond == 8'b00000000 && blockFirst == 8'b00000000) gameFinishFlag = 1; if(blockSecond == 8'b00000000 && blockFirst == 8'b00000000) gameFinishFlag = 1;
end end
// 障礙物右移 // 障礙物右移
barrier = barrier<<1; if(ball_is_on_the_gronud == 0)
if(barrier == 8'b0) begin
barrier = 8'b00000011; barrier = barrier<<1;
if(barrier == 8'b0)
barrier = 8'b00000011;
end
end end
end end
@ -451,18 +454,18 @@ module FPGA_FINAL(
if(count_digit_enable == 0) if(count_digit_enable == 0)
begin begin
count_digit_enable = 1; count_digit_enable = 1;
COM = 2'b01; COM = 4'b1110;
end end
else else
begin begin
count_digit_enable = 0; count_digit_enable = 0;
COM = 2'b10; COM = 4'b1101;
end end
end end
// 顯示個位 // 顯示個位
if(count_digit_enable == 0) if(count_digit_enable == 1)
begin begin
case(count_digit) case(count_digit)
4'b0000:{a,b,c,d,e,f,g}=7'b0000001; 4'b0000:{a,b,c,d,e,f,g}=7'b0000001;