Self adjust the speed of the ball
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32
FPGA_FINAL.v
32
FPGA_FINAL.v
@ -8,7 +8,8 @@ module FPGA_FINAL(
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input show_two_row,
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output testLED,
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output reg a,b,c,d,e,f,g,
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output reg [0:3] COM
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output reg [0:3] COM,
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input highSpeed
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);
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reg [7:0]blockFirst = 8'b11111111;
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@ -65,7 +66,7 @@ module FPGA_FINAL(
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// 開始所有除頻器
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divfreq F(CLK, divclk);
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buttondivfreq BT(CLK, buttonclk);
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buttondivfreq BT(CLK, highSpeed, buttonclk);
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@ -517,16 +518,29 @@ endmodule
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// 按鈕用的除頻器
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module buttondivfreq(input CLK, output reg CLK_div);
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module buttondivfreq(input CLK, highSpeed, output reg CLK_div);
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reg[24:0] Count;
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always @(posedge CLK)
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begin
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if(Count>2500000) // 20 Hz
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begin
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Count <= 25'b0;
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CLK_div <= ~CLK_div;
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end
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if(highSpeed == 0)
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begin
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if(Count>2500000) // 20 Hz
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begin
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Count <= 25'b0;
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CLK_div <= ~CLK_div;
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end
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else
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Count <= Count + 1'b1;
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end
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else
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Count <= Count + 1'b1;
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begin
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if(Count>1000000) // 50 Hz
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begin
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Count <= 25'b0;
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CLK_div <= ~CLK_div;
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end
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else
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Count <= Count + 1'b1;
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end
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end
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endmodule
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