From f2ed938dca049e6cc2c5f3dbe8f70a884642f3c3 Mon Sep 17 00:00:00 2001 From: snsd0805 Date: Sun, 10 Jan 2021 21:03:28 +0800 Subject: [PATCH] =?UTF-8?q?fix:=20=E4=BF=AE=E6=94=B9=E9=80=B2=E4=BD=8D?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- FPGA_FINAL.v | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/FPGA_FINAL.v b/FPGA_FINAL.v index 55f0d3b..1a06ba0 100644 --- a/FPGA_FINAL.v +++ b/FPGA_FINAL.v @@ -211,7 +211,7 @@ module FPGA_FINAL( if(blockSecond[ball_position]==1) begin count_digit <= count_digit + 1'b1; - if(count_digit == 4'b1010) + if(count_digit == 4'b1001) begin count_digit <= 4'b0; count_ten = 1; @@ -235,7 +235,7 @@ module FPGA_FINAL( if(blockFirst[ball_position]==1) begin count_digit <= count_digit + 1'b1; - if(count_digit == 4'b1010) + if(count_digit == 4'b1001) begin count_digit <= 4'b0; count_ten = 1; @@ -323,12 +323,12 @@ module FPGA_FINAL( if(count_digit_enable == 0) begin count_digit_enable = 1; - COM = 2'b10; + COM = 2'b01; end else begin count_digit_enable = 0; - COM = 2'b01; + COM = 2'b10; end end