refactor: 刪除不必要的除頻器
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FPGA_FINAL.v
15
FPGA_FINAL.v
@ -196,18 +196,3 @@ module buttondivfreq(input CLK, output reg CLK_div);
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end
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endmodule
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// 球 飛行用的除頻器
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module balldivfreq(input CLK, output reg CLK_div);
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reg[26:0] Count;
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always @(posedge CLK)
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begin
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if(Count>10000000)
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begin
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Count <= 27'b0;
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CLK_div <= ~CLK_div;
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end
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else
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Count <= Count + 1'b1;
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end
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endmodule
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